A non-volatile memory is a type of memory that retains stored data when power is removed. There are various types of nonvolatile memories including e.g., read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). One type of EEPROM device is a flash EEPROM device (also referred to as “flash memory”).
Two common types of flash memory architectures are the “NAND” and “NOR” architectures, so called for the resemblance which the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuit, respectively. A NAND array architecture arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell are connected by rows to word lines. However, each memory cell is not directly connected to a source line and a bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, 32, or more, where the memory cells in the string are connected together in series, source to drain, between a common source line and a bit line. The NAND architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their gates. In addition, the word lines connected to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by a higher gate voltage so as to operate them as pass transistors, allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the bit line through each floating gate memory cell of the connected string, restricted only by the memory cells of each string that are selected to be read. Thereby, the current encoded stored data values of the row of selected memory cells are placed on the bit lines.
Generally, in a flash memory device, a charged floating gate represents one logic state, e.g., a logic “0”, while a non-charged floating gate represents the opposite logic state e.g., a logic “1”. However, in a multilevel cell, there are three charged logic states, e.g., “00”, “01”, “10”, while a non-charged floating gate is represented by the logic state “11.” A flash memory cell is programmed by placing the floating gate into one of these charged states. Charges may be injected or written onto the floating gate by any number of methods, including e.g., avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron (CHE) injection. The floating gate may be discharged or erased by any number of methods including e.g., Fowler-Nordheim tunneling.
Programming of a flash memory device is typically achieved by biasing (by applying a series of pulses) the drain region to a first voltage, relative to the source region, and biasing the control gate to a second positive voltage which is greater than the first voltage. In the absence of any stored charge on the floating gate, this biasing causes the formation of an inversion-layer channel of electrons, between the source and drain regions. The larger positive bias on the control gate also establishes an electrical field in a tunneling oxide layer. This electric field attracts the electrons and accelerates them toward the floating gate, which is between the control gate and the channel region, by a process known as Fowler-Nordheim tunneling. The floating gate then accumulates and traps the accumulated charge.
The accumulation of a large quantity of trapped charge (electrons) on the floating gate will cause the effective threshold voltage of the field effect transistor comprising the source region, drain region, channel region and control gate to increase. If this increase is sufficiently large, the field effect transistor will remain in a nonconductive off state when a predetermined “read” voltage is applied to the control gate during a read operation. In the programmed state, the flash device may be said to be storing a logic 0 for a single cell flash memory device or logic 0, 01, 10 for a multilevel cell flash memory device. Once programmed, the flash device retains its higher threshold voltage even when its power supply is interrupted or turned off for long periods of time.
In flash memory devices, there is a coupling between the floating gates of neighboring memory cells (referred to as floating gate to floating gate coupling). When a voltage of a floating gate of a memory cell changes, for example to program a memory cell as described above, the voltages of the neighboring cells are also effected due to the coupling. When a memory cell (target cell) is programmed, the voltages of the neighboring memory cells change because the floating gates of its neighboring cells couple with the floating gate of the target cell. The voltage change of the neighboring cells may cause a cell to appear more or less programmed than it actually is, which is undesirable. Accordingly, there is a need and desire to reduce the floating gate to floating gate coupling experienced in today's flash memory devices.